Defect dependent memory switching in amorphous silicon alloys [a-Si xC1-x:H]

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dc.contributor.authorShannon, J. M.
dc.contributor.authorGateru, Robert
dc.contributor.authorGerstner, Ed
dc.date.accessioned2024-11-20T12:44:16Z
dc.date.available2024-11-20T12:44:16Z
dc.date.issued2002
dc.description.abstractIt is shown that memory switching in amorphous silicon alloys is affected by ion bombardment. In particular, ion damage lowers the voltage required to form devices and switch them into the on-state. This technique enables optimised non-volatile memory devices to be made with improved switching ratios.
dc.identifier.citationShannon, J.M.,Gateru, Robert.,& Gerstner, Ed.(2002) Defect dependent memory switching in amorphous silicon alloys [a-Si xC1-x:H] Electronics Letters 38(5):249 - 250
dc.identifier.urihttps://repository.ru.ac.ke/handle/123456789/1473
dc.language.isoen
dc.publisherElectronics Letters
dc.subjectamorphous silicon alloys
dc.subjection bombardment
dc.titleDefect dependent memory switching in amorphous silicon alloys [a-Si xC1-x:H]
dc.typeArticle

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